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| Datasheet File OCR Text: |
| ?products and specifications discussed herein are for evaluation and reference purposes only and are subject to change by aptin a without notice. products are only warranted by aptina to meet aptinas production data sheet specifications. MT9M012: 1/4.5-inch 1.6mp cmos digital image sensor features advance ? pdf: 3846173010/source: 5724337828 aptina reserves the right to change products or specifications without notice. MT9M012_ds - rev. d 5/10 en 1 ?2007 aptina imaging corporation all rights reserved. MT9M012 1/4.5-inch 1.6mp cmos digital image sensor MT9M012 for the latest MT9M012 data sheet, refer to aptinas web site: www.aptina.com features ? digitalclarity ? cmos imaging technology ? maximum frame rate (1280h x 720v/30 fps at 49.5 mhz) ? superior low-light performance ?low dark current ? global reset release (grr), which starts the exposure of all rows simultaneously ? simple two-wire serial interface ? programmable controls: gain , frame rate, frame size, exposure ? horizontal and vertical mirror image ? automatic black level calibration ? on-chip phase-locked loop (pll) oscillator ? bulb exposure mode for arbitrary exposure times ? snapshot mode to take frames on demand ? parallel data output ? electronic rolling shutter (ers), progressive scan ? arbitrary image decimati on with anti-aliasing ?programmable i/o slew rate ? programmable power-down mode (mode a or mode b) ? xenon and led flash support with fast exposure adaptation ? flexible support for external auto focus, optical zoom, and mechanical shutter applications ?pc cameras table 1: key performance parameters ordering information table 2: available part numbers parameter value optical format 1/4.5-inch (4:3) active imager size 3.24mm(h) x 2.41mm(v) active pixels 1472h x 1096v pixel size 2.2 x 2.2 m color filter array rgb bayer pattern shutter type global reset release (grr) (snapshot only), electronic rolling shutter (ers) maximum data rate/master clock 49.5 mp/s / 49.5 mhz frame rate 1440h x 1080v programmable up to 15 fps 1280h x 720v programmable up to 30 fps adc resolution 12-bit, on-chip responsivity 1.4 v/lux-sec dynamic range 70.1db snr max 38.1db supply voltage digital 1.7C1.9v i/o 2.6C3.1v pll 2.6C3.1v analog 2.6C3.1v power consumption 364.6mw at 2.8v operating temperature C30c to +70c packaging die part number description MT9M012d00stc bare die
pdf: 3846173010/source:5724337828 aptina reserves the right to change products or specifications without notice. MT9M012_ds - rev. d 5/10 en 2 ?2007 aptina imaging corporation. all rights reserved. MT9M012: 1/4.5-inch 1.6mp cmos digital image sensor table of contents advance table of contents features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 ordering information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 functional overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 typical connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 pixel array structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 default readout order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 output data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 parallel pixel data interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 output data timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 row timing details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 serial bus description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 start bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 slave address. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 acknowledge bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 no-acknowledge bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 stop bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 bus idle state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 data bit transfer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 two-wire serial interface sample write and read seq uences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 16-bit write sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 16-bit read sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 register notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 bit fields. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 frame sync'd. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 bad frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 register list and default values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 signal chain and datapath . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 gains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 analog gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 digital gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 analog black level calibration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 digital black level calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 pll-generated master clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 pll setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 maintaining a constant frame rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 synchronizing register writes to frame boundaries. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 restart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 window size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 readout modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 mirror mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 column mirror . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 pdf: 3846173010/source:5724337828 aptina reserves the right to change products or specifications without notice. MT9M012_ds - rev. d 5/10 en 3 ?2007 aptina imaging corporation. all rights reserved. MT9M012: 1/4.5-inch 1.6mp cmos digital image sensor table of contents advance row mirror . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 image acquisition modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 electronic rolling shutter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 global reset release . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 exposure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 strobe control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 timing specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 power-up sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 power-down sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 power-up initial commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 hard reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 soft reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 signal state during reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 standby and chip enable (power save mode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 spectral characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 electrical specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 two-wire serial register interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 i/o timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 dc electrical characteristic s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 pdf: 3846173010/source: 5724337828 aptina reserves the right to change products or specifications without notice. MT9M012_ds - rev. d 5/10 en 4 ?2007 aptina imaging corporation. all rights reserved. MT9M012: 1/4.5-inch 1.6mp cmos digital image sensor list of figures advance list of figures figure 1: block diagram ? parallel output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 figure 2: typical configuration ? parallel co nnection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 figure 3: pixel array description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 figure 4: pixel color pattern detail (top right corner) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 figure 5: imaging a scene . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 figure 6: spatial illustration of image readout - parallel inte rface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 figure 7: pixel data timing example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 figure 8: row timing and frame_valid/line_valid signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 figure 9: 1280x720/30 fps row timing details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 figure 10: 1440x1080/15 fps mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 figure 11: timing diagram showing a write to r0x09 with the valu e 0x0284 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 figure 12: timing diagram showing a read from r0x09; returned value 0x0284 . . . . . . . . . . . . . . . . . . . . . . . . .17 figure 13: signal path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 figure 14: pll-generated master clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 figure 15: six pixels in normal and column mirror readout modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 figure 16: six rows in normal and row mi rror readout modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 figure 17: ers snapshot timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 figure 18: grr snapshot timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 figure 19: power supply power-up sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 figure 20: power supply power-down sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 figure 21: typical color spectral characte ristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 figure 22: chief ray angle (cra) vs. image height . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 figure 23: two-wire serial bus timing parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 figure 24: parallel i/o timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 pdf: 3846173010/source: 5724337828 aptina reserves the right to change products or specifications without notice. MT9M012_ds - rev. d 5/10 en 5 ?2007 aptina imaging corporation. all rights reserved. MT9M012: 1/4.5-inch 1.6mp cmos digital image sensor list of tables advance list of tables table 1: key performance parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 table 2: available part numbers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 table 3: signal descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 table 4: pixel type by column . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 table 5: pixel type by row . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 table 6: core register ? register list and default values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 table 7: core registers ? register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 table 8: frequency parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 table 9: operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 table 10: strobe timepoints. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 table 11: power supply power-up timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 table 12: power supply power-down timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 table 13: signal state during reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 table 14: standby modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 table 15: two-wire serial bus characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 table 16: i/o timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 table 17: dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 table 18: power consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 table 19: absolute maximum values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 pdf: 3846173010/source: 5724337828 aptina reserves the right to change products or specifications without notice. MT9M012_ds - rev.d 5/10 en 6 ?2007 aptina imaging corporation. all rights reserved. MT9M012: 1/4.5-inch 1.6mp cmos digital image sensor general description advance general description the aptina MT9M012 is a 1/4.5-inch format cmos active-pixel digital image sensor with a pixel array of 1472h x 1096v. the defaul t active imaging arra y size is 1440 x 1080. it incorporates sophisticated on-chip camera functions such as windowing, mirroring, and snapshot mode. it is programmable thro ugh a simple two-wire serial interface and has very low power consumption. the MT9M012 digital image sensor features digitalclarity?aptina?s breakthrough low- noise cmos imaging technology that achi eves near-ccd image quality (based on signal-to-noise ratio and low-light sensitivity) while maintaining the inherent size, cost, and integration advantages of cmos. functional overview the MT9M012 is a progressive-scan sensor th at generates a stream of pixel data at a constant frame rate. it uses an on-chip, phas e-locked loop (pll) to generate all internal clocks from a single ma ster input clock running between 8 and 18 mhz. user interaction with the sensor is through the two-wire serial bus, which communi- cates with the array control, analog signal chai n, and digital signal chain. the core of the sensor is a 1.6mp active-pixel array. the timing and control circuitry sequences through the rows of the array, resetting and then read ing each row in turn. in the time interval between resetting a row and reading that row, the pixels in the row integrate incident light. the exposure is controlled by varying the time interval between reset and readout. once a row has been read, the data from the colu mns is sequenced through an analog signal chain (providing offset correction and gain), and then through an adc. the output from the adc is a 12-bit value for each pixel in the array. the adc output passes through a digital processing signal chain (which provid es further data path corrections and applies digital gain). the pixel data are output at a rate of up to 49.5 mp/s, in addition to frame and line synchronization signals in parallel mo de corresponding to a pixel clock rate of 49.5 mhz. figure 1 shows the block diagram of the sensor. figure 1: block diagram C parallel output d out [11:0] frame_valid line_valid pixclk sclk sdata reset_bar extclk serial interface array control pixel array 1600h x 1152v data path analog signal chain pdf: 3846173010/source: 5724337828 aptina reserves the right to change products or specifications without notice. MT9M012_ds - rev.d 5/10 en 7 ?2007 aptina imaging corporation. all rights reserved. MT9M012: 1/4.5-inch 1.6mp cmos digital image sensor functional overview advance the pixel array contains optically active and light-shielded (dark) pixels. the dark pixels are used to provide data for on-chip offset correction algorithms (black level control). the sensor contains a set of control and status registers that can be used to control many aspects of the sensor behavior including the frame size, exposure, and gain setting. these registers can be accessed through a two-wire serial interface. the output from the sensor (MT9M012) is a bayer pattern; alternate rows are a sequence of either green and red pixels or blue and gr een pixels. the offset and gain stages of the analog signal chain provide per-color control of the pixel data. a flash strobe output signal is provided to al low an external xenon or led light source to synchronize with the sensor exposure time an d to support the provision of an external mechanical shutter. pdf: 3846173010/source: 5724337828 aptina reserves the right to change products or specifications without notice. MT9M012_ds - rev.d 5/10 en 8 ?2007 aptina imaging corporation. all rights reserved. MT9M012: 1/4.5-inch 1.6mp cmos digital image sensor signal descriptions advance signal descriptions table 3 provides signal descriptions for the MT9M012. table 3: signal descriptions name type description sclk input serial clock. pull to v dd _io with a 1.5k resistor (depending on bus loading). reset_bar input master reset signal, active low. extclk input input clock signal 8C49.5 mhz. trigger input snapshot trigger. used to trigger one frame of output in snapshot modes. test input enables manufacturing test modes. tie to digital gnd for functional operation. s data i/o serial data. pull to v dd _io with a 1.5k resistor (depending on bus loading). strobe output snapshot strobe. driven high when all pixels are exposing in snapshot modes. d out [11:0] output pixel data. pixel data is 12-bit. msb (d out 11) through lsb (d out 0) of each pixel, to be captured on the falling edge of pixclk. pixclk output pixel clock. used to qualify the line_valid (lv), frame_valid (fv), and d out [11:0]. these outputs should be captured on the falling edge of this signal. frame_valid output frame valid. qualified by pixclk. driven high during active pixels and horizontal blanking of each frame and low during vertical blanking. line_valid output line valid output. qualified by pixclk. driven high with active pixels of each line and low during horizontal blanking periods. external pull down resistor to d gnd (typical 10kC100k) required for proper initialization sequence. v dd supply digital power 1.8v nominal. vaa_pix supply pixel array power 2.8v nominal. v aa supply analog power 2.8v nominal. v dd _pll supply pll power 2.8v nominal. v dd _io supply i/o power supply 2.8v nominal. d gnd supply digital ground. a gnd supply analog ground. nc C no connect. pdf: 3846173010/source: 5724337828 aptina reserves the right to change products or specifications without notice. MT9M012_ds - rev.d 5/10 en 9 ?2007 aptina imaging corporation. all rights reserved. MT9M012: 1/4.5-inch 1.6mp cmos digital image sensor typical connections advance typical connections figure 2 shows typical connections for the MT9M012 sensor. for low-noise operation, the MT9M012 requires separate power supplies for analog and digital. incoming digital and analog ground conductors can be tied to gether next to the die. both power supply rails should be decoupled from ground using capacitors as close as possible to the die. the use of inductance filters is not recommended on the power supplies or output signals. the MT9M012 also supports different digital core (v dd /d gnd ) and i/o power (v dd _io/ d gnd ) power domains that can be at different voltages. pll requires a clean power source (v dd _pll). figure 2: typical configuration C parallel connection notes: 1. typical connection shows only one scenario out of multiple possible variations for this sensor. 2. all inputs must be configured with v dd _io. 3. v aa and vaa_pix must be tied together. d out [11:0] frame_valid pixclk strobe line_valid nc reset_bar sclk s data trigger extclk v dd _io v dd v dd _pll v aa _pix v aa a gnd 10k 1.5k v dd _io v dd v dd _pll v aa 1f test d gnd from controller master clock to image processor (open) 1.5k 10k pdf: 3846173010/source: 5724337828 aptina reserves the right to change products or specifications without notice. MT9M012_ds - rev.d 5/10 en 10 ?2007 aptina imaging corporation. all rights reserved. MT9M012: 1/4.5-inch 1.6mp cmos digital image sensor pixel array structure advance pixel array structure the MT9M012 pixel array consists of a 160 0-column by 1152-row matrix of pixels addressed by column and row. the address (column 0, row 0) represents the upper-right corner of the entire array, looking at the sensor, as shown in figure 3. the array consists of a 1440-column by 1080-ro w active region in the center representing the default output image resolution, surrounded by a boundary region (also active), surrounded by a border of dark pixels (see table 4 and table 5). the boundary region can be used to avoid edge effects when doing color processing, while the optically black column and rows can be used to monitor the black level. default readout order by convention, the sensor core pixel array is shown with pixel (0, 0) in the top right corner (see figure 3). this reflects the actual layout of the array on the die. also, the first pixel data read out of the sensor in defa ult condition is that of pixel (16, 60). figure 3: pixel array description table 4: pixel type by column column pixel type 0C15 active boundary (16) 16C1455 active image (1440) 1456C1471 active boundary (16) 1472C1599 black (128) table 5: pixel type by row row pixel type 0C51 black (52) 53C59 active boundary (8) 60C1139 active image (1,080) 1140C1147 active boundary (8) 1148C1151 black (4) (1599, 1151) 0 black columns 4 black rows 52 black rows (0, 0) 128 black columns active image 1440 x 1080 active pixels (16, 60) (1455, 1139) pdf: 3846173010/source: 5724337828 aptina reserves the right to change products or specifications without notice. MT9M012_ds - rev.d 5/10 en 11 ?2007 aptina imaging corporation. all rights reserved. MT9M012: 1/4.5-inch 1.6mp cmos digital image sensor pixel array structure advance sensor pixels are output in a bayer pattern format consisting of four ?colors??greenr, greenb, red, and blue (gr, gb, r, b)?represe nting three filter colors. when no mirror modes are enabled, even-numbered rows contain alternate green1 and red pixels; odd- numbered rows contain alternate blue and green2 pixels. even-numbered columns contain greenr and blue pixels; odd-numbered columns contain red and greenb pixels. the greenr and greenb pixels have the same color filter, but they are treated as separate colors by the data path and analog signal chain. figure 4: pixel color pattern detail (top right corner) when the sensor is imaging, the active surface of the sensor faces the scene, as shown in figure 5. when the image is read out of the se nsor, it is read one row at a time, with the rows and columns sequenced, as shown in figure 4. figure 5: imaging a scene first clear pixel (0,52) black pixels column readout direction . . . . . . ... row readout direction r gb r gb r gb gr b gr b gr b r gb r gb r gb gr b gr b gr b r gb r gb r gb gr b gr b gr b lens pixel (0,0) row readout order column readout order scene sensor (rear view) pdf: 3846173010/source: 5724337828 aptina reserves the right to change products or specifications without notice. MT9M012_ds - rev.d 5/10 en 12 ?2007 aptina imaging corporation. all rights reserved. MT9M012: 1/4.5-inch 1.6mp cmos digital image sensor output data format advance output data format parallel pixel data interface MT9M012 image data is read out in a progre ssive scan. valid image data is surrounded by horizontal blanking and vertical blanking, as shown in figure 6. the amount of hori- zontal blanking and vertical blanking is pr ogrammable; lv is high during the shaded region of figure 6. fv timing is described in the next section. figure 6: spatial illustration of image readout - parallel interface p 0,0 p 0,1 p 0,2 .....................................p 0,n-1 p 0,n p 1,0 p 1,1 p 1,2 .....................................p 1,n-1 p 1,n 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 p m-1,0 p m-1,1 .....................................p m-1,n-1 p m-1,n p m,0 p m,1 .....................................p m,n-1 p m,n 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 00 00 00 ..................................... 00 00 00 00 00 00 ..................................... 00 00 00 00 00 00 ..................................... 00 00 00 00 00 00 ..................................... 00 00 00 valid image horizontal blanking vertical blanking vertical/horizontal blanking pdf: 3846173010/source: 5724337828 aptina reserves the right to change products or specifications without notice. MT9M012_ds - rev.d 5/10 en 13 ?2007 aptina imaging corporation. all rights reserved. MT9M012: 1/4.5-inch 1.6mp cmos digital image sensor output data timing advance output data timing the sensor core output data is synchronized with the pixclk output. when line_valid is high, one pixel data is output on the 12-bit d out output every pixclk period. by default, the internal pll is used and pixclk runs at the 2x master clock. the falling edge of pixclk appears at the center of the d out . this allows pixclk to be used as a clock to sample the data. by default, pixclk is not enabled, and its on or off is register controllable. when on, pixclk is continuously enabled, even during the blanking period. the MT9M012 can be programmed to delay the pixclk edge relative to the d out transitions. this can be achieved by programming the corresponding register bits. figure 7: pixel data timing example figure 8: row timing and frame_valid/line_valid signals the sensor timing is shown in terms of pixel clock and master clock cycles (figure 7 and figure 8). p 0 [11:0] p 1 [11:0] p 2 [11:0] p 3 [11:0] p 4 [11:0] p 5 p n-2 p n-1 [11:0] p n [11:0] valid image data blanking blankin g line_valid pixclk dout(11:0) frame_valid line_valid number of master clocks p a q aqap pdf: 3846173010/source: 5724337828 aptina reserves the right to change products or specifications without notice. MT9M012_ds - rev.d 5/10 en 14 ?2007 aptina imaging corporation. all rights reserved. MT9M012: 1/4.5-inch 1.6mp cmos digital image sensor output data timing advance row timing details this section discusses row timing for 1440 x 1080 15 fps and 1280 x 720 30 fps modes. in figure 9 and figure 10, h-bl is horizontal blan king, ob is optically black columns, h is one row, and v-bl is vertical blanking. th e pixel clock is two times the array clock (pclk = 49.5 mhz, aclk = 24.75 mhz). each pc lk outputs one active pixel or one black pixel. h-bl setting value uses aclk as a unit (one horizontal blank needs two pclks). figure 9: 1280x720/30 fps row timing details ? aclk = 24.75 mhz h = h ? bl + active cols/2+ ob/2 h = 404 aclks + 656 aclks + 40 aclks = 1100 aclks = 44.44 s ? v = 14h + 736h = 750h t frame = h x v = 1100 x750 = 825000 aclks = 825000 aclks/24.75 mhz = 33.33ms ? frame rate = 1/ t frame = 1/33.33ms = 30 fps ? active readout window is 1312 (1280+32 boundry) columns x 736 (720+16 boundry) rows figure 10: 1440x1080/15 fps mode ? aclk = 24.75 mhz ? h = h-bl + active cols/2 + ob/2 = 424 aclks + 736 aclks + 40 aclks = 1200 aclks = 48.48 s ? v = 279h + 1096h = 1375h ? t frame = h x v = 1200 x 1375 = 1650000 aclks = 1650000 aclks/24.75 mhz = 66.66ms ? frame rate = 1/ t frame = 1/66.66ms = 15 fps ? active readout window is 1472 (1440+32 boundry) columns x 1096 (1080+16 boundry) rows 1h 404mclk 656mclk 40mclk h-bl active 1312 cols 80 ob 14h 736h v-bl a ctive rows 1h 424mclk 736mclk 40mclk h-bl active 1472 cols 80 ob 279h 1096h v-bl active rows pdf: 3846173010/source: 5724337828 aptina reserves the right to change products or specifications without notice. MT9M012_ds - rev.d 5/10 en 15 ?2007 aptina imaging corporation. all rights reserved. MT9M012: 1/4.5-inch 1.6mp cmos digital image sensor serial bus description advance serial bus description registers are written to and read from the MT9M012 through the two-wire serial inter- face bus. the MT9M012 is a serial interface slave and is controlled by the serial clock (sclk), which is driven by the serial interface master. data is transferred into and out of the MT9M012 through the serial data (s data ) line. the s data line is pulled up to v dd _io off-chip by a 1.5k resistor. either the slave or master device can pull the s data line low?the serial interface protocol determines which device is allowed to pull the s data line down at any given time. protocol data transfers on the two-wire serial interf ace bus are performed by a sequence of low level protocol elements: ?a start bit ? the slave device 8-bit address ? an (a no) acknowledge bit ? an 8-bit message ?a stop bit start bit the start bit is defined as a high-to-low transi tion of the data line while the clock line is high. slave address the 8-bit address of a two-wire serial interfac e device consists of 7 bits of address and 1 bit of direction. a ?0? in the lsb (least sign ificant bit) of the address indicates write mode (0xb8), and a ?1? indicates read mode (0xb9). the two-wire serial interface device addr esses consists of 7 bits. for the MT9M012 sensor (parallel interface), th e device is fixed at [1011100]. acknowledge bit the master generates the acknowledge clock pu lse. the transmitter (which is the master when writing, or the slave when reading) re leases the data line, and the receiver indi- cates an acknowledge bit by pulling the data line low during the acknowledge clock pulse. no-acknowledge bit the no-acknowledge bit is generated when the data line is not pulled down by the receiver during the acknowledge clock pulse. a no-acknowledge bit is used to terminate a read sequence. stop bit the stop bit is defined as a low-to-high transi tion of the data line while the clock line is high. pdf: 3846173010/source: 5724337828 aptina reserves the right to change products or specifications without notice. MT9M012_ds - rev.d 5/10 en 16 ?2007 aptina imaging corporation. all rights reserved. MT9M012: 1/4.5-inch 1.6mp cmos digital image sensor serial bus description advance sequence a typical read or write sequence begins by th e master sending a start bit. after the start bit, the master sends the slave device's 8-bi t address. the last bit of the address deter- mines if the request is a read or a write, where a ?0? indicates a write and a ?1? indi- cates a read. the slave device acknowledges its address by sending an acknowledge bit back to the master. if the request was a write, the master then transfers the 8-bit register address to which a write should take place. the slave sends an acknowledge bit to indicate that the register address has been received. the master then transfers the data 8 bits at a time, with the slave sending an acknowledge bit after each 8 bits. the MT9M012 uses 16-bit data for its internal registers, thus requiring two 8-bit transfers to write to one register. after 16 bits are transferred, the register ad dress is automatically incremented, so that the next 16 bits are written to the next regi ster address. the master stops writing by sending a start or stop bit. a typical read sequence is executed as foll ows. first the master sends the write-mode slave address and 8-bit register address, just as in the write request. the master then sends a start bit and the read-mode slave address. the master then clocks out the register data 8 bits at a time. the master sends an acknowledge bit after each 8-bit transfer. the register address is automatically incremented after every 16 bits is trans- ferred. the data transfer is stopped when the master sends a no-acknowledge bit. bus idle state the bus is idle when both the data and cloc k lines are high. control of the bus is initi- ated with a start bit, and the bus is released with a stop bit. only the master can generate the start and stop bits. data bit transfer one data bit is transferred during each clock pulse. the serial interface clock pulse is provided by the master. the data must be stab le during the high period of the two-wire serial interface clock?it can only change wh en the serial clock is low. data is trans- ferred 8 bits at a time, foll owed by an acknowledge bit. pdf: 3846173010/source: 5724337828 aptina reserves the right to change products or specifications without notice. MT9M012_ds - rev.d 5/10 en 17 ?2007 aptina imaging corporation. all rights reserved. MT9M012: 1/4.5-inch 1.6mp cmos digital image sensor two-wire serial interface sample write and read sequences advance two-wire serial interface sample write and read sequences 16-bit write sequence a typical write sequence for writing 16 bits to a register is shown in figure 11. a start bit given by the master, followed by the write address, starts the sequence. the image sensor then sends an acknowledge bit and expects the register address to come first, followed by the 16-bit data. after each 8-bit transfer, the image sensor sends an acknowledge bit. all 16 bits must be written before the register is updated. after 16 bits are transferred, the register address is automatically incremented so that the next 16 bits are written to the next register. the master stops writ ing by sending a start or stop bit. figure 11: timing diagram showing a write to r0x09 with the value 0x0284 16-bit read sequence a typical read sequence is shown in figure 12. first the master has to write the register address, as in a write sequence. then a start bit and the read address specify that a read is about to happen from the register. the master then clocks out the register data 8 bits at a time. the master sends an acknowledge bit after each 8-bit transfer. the register address is incremented after every 16 bits is transferred. the data transfer is stopped when the master sends a no-acknowledge bit. figure 12: timing diagram showing a read from r0x09; returned value 0x0284 sclk s data start ack 0xb8 addr ack ack ack stop r0x09 1000 0100 0000 0010 sclk s data start ack 0xb8 addr 0xb9 addr 0000 0010 r0x09 ack ack ack stop 1000 0100 nack start pdf: 3846173010/source: 5724337828 aptina reserves the right to change products or specifications without notice. MT9M012_ds - rev.d 5/10 en 18 ?2007 aptina imaging corporation. all rights reserved. MT9M012: 1/4.5-inch 1.6mp cmos digital image sensor registers advance registers register map register notation in this document, registers are described either by address or by name. table 6 on page 19 and table 7 on page 24 show the loca tions used within the address space. loca- tions that are not shown in the table are reserved for future use; they should not be read from or written to in order to maintain comp atibility with future designs. locations that are shown as ?reserved? should not be accessed. the default read values of these regis- ters are subject to change. caution the effect of writing to reserved registers is undefined and may include the possibility of causing permanent electrical damage to the sensor. bit fields some registers provide control of several different pieces of related functionality, and this makes it necessary to refer to bit fields within registers. as an example of the nota- tion used for this, the least significant 4 bits of the chip version register are referred to as r0x0000[3:0]. frame sync'd frame start is defined as the point at which the first dark row is read out internally to the sensor. in the register tables the ?sync?d? co lumn shows which registers or register fields are frame sync?d (with f attributes). bad frames a bad frame is a frame where all rows do no t have the same integration time or where offsets to the pixel values have changed du ring the frame.many changes to the sensor register settings can cause a bad frame. for example, when row size (r0x003) is changed, the new register value does not af fect sensor behavior until the next frame start. however, the frame that would be read out at that frame start will have been inte- grated using the old row size, so reading it out using the new row width would result in a frame with an incorrect integration time. by default, bad frames are not masked. if th e masked bad frame option is enabled, both lv and fv are inhibited for these frames so that the vertical blanking time between frames is extended by the frame time. in the register tables, the ?bad frame? column shows where changing a register or register field will cause a bad frame (with bf attri- butes). the following notation is used: n?no. changing the register value will not produce a bad frame. y?yes. changing the register value might produce a bad frame. pdf: 3846173010/source: 5724337828 aptina reserves the right to change products or specifications without notice. MT9M012_ds - rev.d 5/10 en 19 ?2007 aptina imaging corporation. all rights reserved. MT9M012: 1/4.5-inch 1.6mp cmos digital image sensor register list and default values advance register list and default values table 6: core register C register list and default values 1 = read-only, always 1; 0 = read-only, always 0; d = programmable; ? = read-only, dynamic; C = undefined after reset register # dec (hex) register description data format (binary) default value dec (hex) r0:0(r0x000) chip version ???? ???? ???? ???? 5122 (0x1402) r1:0(r0x001) row start 0000 0ddd dddd dddd 60 (0x003c) r2:0(r0x002) column start 0000 dddd dddd dddd 16 (0x0010) r3:0(r0x003) row size 0000 0ddd dddd dddd 1079 (0x0437) r4:0(r0x004) column size 0000 dddd dddd dddd 1439 (0x059f) r5:0(r0x005) horizontal blank 0000 dddd dddd dddd 0 (0x0000) r6:0(r0x006) vertical blank 0000 0ddd dddd dddd 8 (0x0008) r7:0(r0x007) output control dd0d dddd dddd dddd 40834 (0x9f82) r8:0(r0x008) shutter width upper 0ddd dddd 0000 dddd 0 (0x0000) r9:0(r0x009) shutter width lower dddd dddd dddd dddd 800 (0x0320) r10:0(r0x00a) pixel clock control d0dd 0ddd 0ddd dddd 0 (0x0000) r11:0(r0x00b) restart 0000 0000 0000 dddd 0 (0x0000) r12:0(r0x00c) shutter delay 000d dddd dddd dddd 0 (0x0000) r13:0(r0x00d) reset 0000 0000 0000 000d 0 (0x0000) r15:0(r0x00f) reserved C 0 (0x0000) r16:0(r0x010) reserved C 83 (0x0053) r17:0(r0x011) pll config 1 dddd dddd 00dd dddd 15364 (0x3c04) r18:0(r0x012) reserved C 0 (0x0000) r20:0(r0x014) reserved C 54 (0x0036) r21:0(r0x015) reserved C 16 (0x0010) r30:0(r0x01e) read mode 1 dddd dddd dddd dddd 326 (0x0146) r32:0(r0x020) read mode 2 dddd d000 0ddd dddd 64 (0x0040) r34:0(r0x022) reserved C 0 (0x0000) r35:0(r0x023) reserved C 0 (0x0000) r36:0(r0x024) reserved C 2 (0x0002) r37:0(r0x025) reserved C 518 (0x0206) r38:0(r0x026) reserved C 151 (0x0097) r39:0(r0x027) reserved C 11 (0x000b) r41:0(r0x029) reserved C 1153 (0x0481) r42:0(r0x02a) reserved C 4230 (0x1086) r43:0(r0x02b) green1 gain 0ddd dddd dddd dddd 16 (0x0010) r44:0(r0x02c) blue gain 0ddd dddd dddd dddd 16 (0x0010) r45:0(r0x02d) red gain 0ddd dddd dddd dddd 16 (0x0010) r46:0(r0x02e) green2 gain 0ddd dddd dddd dddd 16 (0x0010) r48:0(r0x030) reserved C 0 (0x0000) r50:0(r0x032) reserved C 0 (0x0000) r53:0(r0x035) global gain dddd dddd dddd dddd 16 (0x0010) r60:0(r0x03c) reserved C 26 (0x001a) r61:0(r0x03d) reserved C 7 (0x0007) r62:0(r0x03e) reserved C 135 (0x0087) r63:0(r0x03f) reserved C 0 (0x0000) r64:0(r0x040) reserved C 7 (0x0007) pdf: 3846173010/source: 5724337828 aptina reserves the right to change products or specifications without notice. MT9M012_ds - rev.d 5/10 en 20 ?2007 aptina imaging corporation. all rights reserved. MT9M012: 1/4.5-inch 1.6mp cmos digital image sensor register list and default values advance r65:0(r0x041) reserved C 3 (0x0003) r66:0(r0x042) reserved C 5 (0x0005) r67:0(r0x043) reserved C 1 (0x0001) r68:0(r0x044) reserved C 515 (0x0203) r69:0(r0x045) reserved C 4112 (0x1010) r70:0(r0x046) reserved C 4112 (0x1010) r71:0(r0x047) reserved C 4112 (0x1010) r72:0(r0x048) reserved C 16 (0x0010) r73:0(r0x049) row black target 0000 dddd dddd dddd 168 (0x00a8) r74:0(r0x04a) reserved C 16 (0x0010) r75:0(r0x04b) row black default offset 0000 dddd dddd dddd 40 (0x0028) r76:0(r0x04c) reserved C 16 (0x0010) r77:0(r0x04d) reserved C 38 (0x0026) r78:0(r0x04e) reserved C 4112 (0x1010) r79:0(r0x04f) reserved C 23 (0x0017) r80:0(r0x050) reserved C 32768 (0x8000) r81:0(r0x051) reserved C 7 (0x0007) r82:0(r0x052) reserved C 32768 (0x8000) r83:0(r0x053) reserved C 7 (0x0007) r84:0(r0x054) reserved C 8 (0x0008) r86:0(r0x056) reserved C 32 (0x0020) r87:0(r0x057) reserved C 10 (0x000a) r88:0(r0x058) reserved C 32768 (0x8000) r89:0(r0x059) reserved C 7 (0x0007) r90:0(r0x05a) reserved C 7 (0x0007) r91:0(r0x05b) blc_sample_size 0000 0000 0000 000d 1 (0x0001) r92:0(r0x05c) blc_tune_1 0000 dddd dddd dddd 90 (0x005a) r93:0(r0x05d) blc_delta_thresholds 0ddd dddd 0ddd dddd 11539 (0x2d13) r94:0(r0x05e) blc_tune_2 0ddd 000d dddd dddd 16895 (0x41ff) r95:0(r0x05f) blc_target_thresholds 0ddd dddd 0ddd dddd 8989 (0x231d) r96:0(r0x060) green1_offset 0000 000d dddd dddd 32 (0x0020) r97:0(r0x061) green2_offset 0000 000d dddd dddd 32 (0x0020) r98:0(r0x062) black_level_calibration dddd d000 0000 00dd 0 (0x0000) r99:0(r0x063) red_offset 0000 000d dddd dddd 32 (0x0020) r100:0(r0x064) blue_offset 0000 000d dddd dddd 32 (0x0020) r101:0(r0x065) reserved C 0 (0x0000) r104:0(r0x068) reserved C 0 (0x0000) r105:0(r0x069) reserved C 0 (0x0000) r106:0(r0x06a) reserved C 0 (0x0000) r107:0(r0x06b) reserved C 0 (0x0000) r108:0(r0x06c) reserved C 0 (0x0000) r109:0(r0x06d) reserved C 0 (0x0000) r112:0(r0x070) reserved C 124 (0x007c) r113:0(r0x071) reserved C 31492 (0x7b04) table 6: core register C register list and default values (continued) 1 = read-only, always 1; 0 = read-only, always 0; d = programmable; ? = read-only, dynamic; C = undefined after reset register # dec (hex) register description data format (binary) default value dec (hex) pdf: 3846173010/source: 5724337828 aptina reserves the right to change products or specifications without notice. MT9M012_ds - rev.d 5/10 en 21 ?2007 aptina imaging corporation. all rights reserved. MT9M012: 1/4.5-inch 1.6mp cmos digital image sensor register list and default values advance r114:0(r0x072) reserved C 30726 (0x7806) r115:0(r0x073) reserved C 5128 (0x1408) r116:0(r0x074) reserved C 5642 (0x160a) r117:0(r0x075) reserved C 13836 (0x360c) r118:0(r0x076) reserved C 19000 (0x4a38) r119:0(r0x077) reserved C 19510 (0x4c36) r120:0(r0x078) reserved C 30544 (0x7750) r121:0(r0x079) reserved C 31234 (0x7a02) r122:0(r0x07a) reserved C 30980 (0x7904) r123:0(r0x07b) reserved C 30726 (0x7806) r124:0(r0x07c) reserved C 30726 (0x7806) r125:0(r0x07d) reserved C 31744 (0x7c00) r126:0(r0x07e) reserved C 31240 (0x7a08) r127:0(r0x07f) reserved C 31236 (0x7a04) r128:0(r0x080) reserved C 25 (0x0019) r129:0(r0x081) reserved C 5892 (0x1704) r130:0(r0x082) reserved C 0 (0x0000) r131:0(r0x083) reserved C 5638 (0x1606) r132:0(r0x084) reserved C 7432 (0x1d08) r134:0(r0x086) reserved C 4870 (0x1306) r135:0(r0x087) reserved C 4360 (0x1108) r144:0(r0x090) reserved C 1140 (0x0474) r145:0(r0x091) reserved C 0 (0x0000) r146:0(r0x092) reserved C 1 (0x0001) r147:0(r0x093) reserved C 0 (0x0000) r148:0(r0x094) reserved C 10510 (0x290e) r154:0(r0x09a) reserved C 0 (0x0000) r155:0(r0x09b) reserved C 0 (0x0000) r156:0(r0x09c) reserved C 0 (0x0000) r157:0(r0x09d) formatter0 dddd dddd dddd dddd 8789 (0x2255) r158:0(r0x09e) formatter1 000d 00dd 00dd dddd 286 (0x011e) r159:0(r0x09f) formatter2 dddd 0000 0111 0001 113 (0x0071) r160:0(r0x0a0) reserved C 0 (0x0000) r161:0(r0x0a1) reserved C 0 (0x0000) r162:0(r0x0a2) reserved C 0 (0x0000) r163:0(r0x0a3) reserved C 0 (0x0000) r164:0(r0x0a4) reserved C 0 (0x0000) r165:0(r0x0a5) reserved C 0 (0x0000) r166:0(r0x0a6) reserved C 0 (0x0000) r167:0(r0x0a7) reserved C 0 (0x0000) r168:0(r0x0a8) reserved C 0 (0x0000) r169:0(r0x0a9) reserved C 0 (0x0000) r170:0(r0x0aa) reserved C 0 (0x0000) r171:0(r0x0ab) reserved C 0 (0x0000) table 6: core register C register list and default values (continued) 1 = read-only, always 1; 0 = read-only, always 0; d = programmable; ? = read-only, dynamic; C = undefined after reset register # dec (hex) register description data format (binary) default value dec (hex) pdf: 3846173010/source: 5724337828 aptina reserves the right to change products or specifications without notice. MT9M012_ds - rev.d 5/10 en 22 ?2007 aptina imaging corporation. all rights reserved. MT9M012: 1/4.5-inch 1.6mp cmos digital image sensor register list and default values advance r172:0(r0x0ac) reserved C 0 (0x0000) r173:0(r0x0ad) reserved C 0 (0x0000) r174:0(r0x0ae) reserved C 32 (0x0020) r175:0(r0x0af) reserved C 0 (0x0000) r176:0(r0x0b0) reserved C 0 (0x0000) r177:0(r0x0b1) reserved C 0 (0x0000) r178:0(r0x0b2) reserved C 0 (0x0000) r179:0(r0x0b3) reserved C 0 (0x0000) r180:0(r0x0b4) reserved C 0 (0x0000) r181:0(r0x0b5) reserved C 0 (0x0000) r182:0(r0x0b6) reserved C 0 (0x0000) r183:0(r0x0b7) reserved C 0 (0x0000) r184:0(r0x0b8) reserved C 0 (0x0000) r185:0(r0x0b9) reserved C 0 (0x0000) r186:0(r0x0ba) reserved C 0 (0x0000) r187:0(r0x0bb) reserved C 0 (0x0000) r188:0(r0x0bc) reserved C 0 (0x0000) r189:0(r0x0bd) reserved C 0 (0x0000) r190:0(r0x0be) reserved C 0 (0x0000) r191:0(r0x0bf) reserved C 0 (0x0000) r192:0(r0x0c0) reserved C 0 (0x0000) r193:0(r0x0c1) reserved C 0 (0x0000) r194:0(r0x0c2) reserved C 0 (0x0000) r195:0(r0x0c3) reserved C 0 (0x0000) r196:0(r0x0c4) reserved C 0 (0x0000) r197:0(r0x0c5) reserved C 0 (0x0000) r198:0(r0x0c6) reserved C 0 (0x0000) r199:0(r0x0c7) reserved C 0 (0x0000) r200:0(r0x0c8) reserved C 0 (0x0000) r201:0(r0x0c9) reserved C 0 (0x0000) r202:0(r0x0ca) reserved C 0 (0x0000) r203:0(r0x0cb) reserved C 0 (0x0000) r204:0(r0x0cc) reserved C 0 (0x0000) r205:0(r0x0cd) reserved C 0 (0x0000) r206:0(r0x0ce) reserved C 0 (0x0000) r207:0(r0x0cf) reserved C 0 (0x0000) r208:0(r0x0d0) reserved C 0 (0x0000) r209:0(r0x0d1) reserved C 0 (0x0000) r210:0(r0x0d2) reserved C 0 (0x0000) r211:0(r0x0d3) reserved C 0 (0x0000) r212:0(r0x0d4) reserved C 0 (0x0000) r213:0(r0x0d5) reserved C 0 (0x0000) r214:0(r0x0d6) reserved C 0 (0x0000) r215:0(r0x0d7) reserved C 0 (0x0000) table 6: core register C register list and default values (continued) 1 = read-only, always 1; 0 = read-only, always 0; d = programmable; ? = read-only, dynamic; C = undefined after reset register # dec (hex) register description data format (binary) default value dec (hex) pdf: 3846173010/source: 5724337828 aptina reserves the right to change products or specifications without notice. MT9M012_ds - rev.d 5/10 en 23 ?2007 aptina imaging corporation. all rights reserved. MT9M012: 1/4.5-inch 1.6mp cmos digital image sensor register list and default values advance r216:0(r0x0d8) reserved C 0 (0x0000) r217:0(r0x0d9) reserved C 0 (0x0000) r218:0(r0x0da) reserved C 0 (0x0000) r219:0(r0x0db) reserved C 0 (0x0000) r220:0(r0x0dc) reserved C 0 (0x0000) r221:0(r0x0dd) reserved C 0 (0x0000) r222:0(r0x0de) reserved C 0 (0x0000) r223:0(r0x0df) reserved C 0 (0x0000) r224:0(r0x0e0) reserved C 0 (0x0000) r225:0(r0x0e1) reserved C 0 (0x0000) r226:0(r0x0e2) reserved C 0 (0x0000) r227:0(r0x0e3) reserved C 0 (0x0000) r228:0(r0x0e4) reserved C 0 (0x0000) r229:0(r0x0e5) reserved C 0 (0x0000) r230:0(r0x0e6) reserved C 0 (0x0000) r231:0(r0x0e7) reserved C 0 (0x0000) r232:0(r0x0e8) reserved C 0 (0x0000) r233:0(r0x0e9) reserved C 0 (0x0000) r234:0(r0x0ea) reserved C 0 (0x0000) r235:0(r0x0eb) reserved C 0 (0x0000) r236:0(r0x0ec) reserved C 0 (0x0000) r237:0(r0x0ed) reserved C 0 (0x0000) r238:0(r0x0ee) reserved C 0 (0x0000) r239:0(r0x0ef) reserved C 0 (0x0000) r240:0(r0x0f0) reserved C 0 (0x0000) r241:0(r0x0f1) reserved C 0 (0x0000) r248:0(r0x0f8) reserved C 1 (0x0001) r250:0(r0x0fa) reserved C 0 (0x0000) r251:0(r0x0fb) reserved C 0 (0x0000) r252:0(r0x0fc) reserved C 0 (0x0000) r253:0(r0x0fd) reserved C 0 (0x0000) r255:0(r0x0ff) chip_version_alt ???? ???? ???? ???? 5122 (0x1402) table 6: core register C register list and default values (continued) 1 = read-only, always 1; 0 = read-only, always 0; d = programmable; ? = read-only, dynamic; C = undefined after reset register # dec (hex) register description data format (binary) default value dec (hex) pdf: 3846173010/source: 5724337828 aptina reserves the right to change products or specifications without notice. MT9M012_ds - rev.d 5/10 en 24 ?2007 aptina imaging corporation. all rights reserved. MT9M012: 1/4.5-inch 1.6mp cmos digital image sensor register descriptions advance register descriptions table 7: core registers C register description register # dec hex bits default name frame sync'd bad frame r0:0 r0x000 15:0 0x1402 chip version (ro) chip version. r1:0 r0x001 15:0 0x003c row start (r/w) y y the y coordinate of the upper-left corner of the fov. if this register is set to an odd value, the next lower even value will be used. r2:0 r0x002 15:0 0x0010 column start (r/w) y n the x coordinate of the upper-left corner of the fov. r3:0 r0x003 15:0 0x0437 row size (r/w) y y the height of the fov minus one. if this register is set to an even value, the next higher odd value will be used. r4:0 r0x004 15:0 0x059f column size (r/w) y y the width of the fov minus one. if this register is set to an even value, the next higher odd value will be used. r5:0 r0x005 15:0 0x0000 horizontal blank (r/w) y y extra time added to the end of each row, in pixel clocks. incrementing this register will increase exposure and decrease frame rate. setting a value less than the minimum will use the minimum horizontal blank. the minimum horizontal blank depends on the mode of the sensor. r6:0 r0x006 15:0 0x0008 vertical blank (r/w) y n extra time added to the end of each frame in rows minus one. incrementing this register will decrease frame rate, but not affect exposure. setting a value less than the minimum will use the minimum vertical blank. r7:0 r0x007 15:0 0x9f82 output control (r/w) 15 0x0001 reserved 14 0x0000 reserved 13 x reserved 12:10 0x0007 reserved 9:7 0x0007 reserved 6 0x0000 reserved 5:4 x reserved 3 0x0000 reserved 2 0x0000 reserved pdf: 3846173010/source: 5724337828 aptina reserves the right to change products or specifications without notice. MT9M012_ds - rev.d 5/10 en 25 ?2007 aptina imaging corporation. all rights reserved. MT9M012: 1/4.5-inch 1.6mp cmos digital image sensor register descriptions advance r7:0 r0x007 1 0x0001 chip enable when this bit is cleared, sensor readout is stopped and analog circuitry is put in a state which draws minimal power. when this bit is set, the chip operates according to the current mode. writing this bit does not affect the values of any other registers. mirrored on r241[0]. to protect chip enable operation from abnormal color shift, apply the following procedure: before chip enable is cleared, set register r0x0b = 0x0003; before chip enable is set, set register r0x0b = 0x0000. nn 0 0x0000 synchronize changes when set, changes to certain registers (those with the sc attribute) are delayed until the bit is clear. when cleared, all the delayed writes will happen immediately. registers with the f attribute will still have the update synchronized to the next frame boundary. mirrored on r241[1]. nn r8:0 r0x008 15:0 0x0000 shutter width upper (r/w) 15 x reserved 14:8 0x0000 dark col sample start the start point for sampling 8 pixels of dark columns which follow pixel data. if the value is larger than 72(0x48), it will automatically be set to 0. yn 7:4 x reserved 3:0 0x0000 shutter width upper the most significant bits of the shutter width, which are combined with shutter width lower (r9). yn the most significant bits of the shutter width, which are combined with shutter width lower (r9). r9:0 r0x009 15:0 0x0320 shutter width lower (r/w) y n the least significant bits of the shutter width. this is combined with shutter_width_upper and shutter_delay such that the effective shutter width is (((((shutter_width_upper) * 6 5536) + shutter_width_lower) * t_row) - shutter_delay - c) in pixclks. this should allow a shutter width from about 40?s to about 40s at default row time. if set to zero, a value of 1 will be used. in ers bulb mode, shutter width has to be greater than or equal to 3. table 7: core registers C register description (continued) register # dec hex bits default name frame sync'd bad frame pdf: 3846173010/source: 5724337828 aptina reserves the right to change products or specifications without notice. MT9M012_ds - rev.d 5/10 en 26 ?2007 aptina imaging corporation. all rights reserved. MT9M012: 1/4.5-inch 1.6mp cmos digital image sensor register descriptions advance r10:0 r0x00a 15:0 0x0000 pixel clock control (r/w) 15 0x0000 invert pixel clock when set, lv, fv, and d out should be captured on the rising edge of pixclk. when clear, they should be captured on the falling edge. this is accomplished by inverting the pixclk output. nn 14 x reserved 13:12 0x0000 power down mode standby mode b on/off. standby mode a, which is set by chip enable (r7 bit 1), supersedes these bits. 0: normal operation (default mode: sensor continues outputting images) 1: standby mode b (sensor powers down) 2: reserved 3: reserved nn 11 x reserved 10:8 0x0000 shift pixel clock two's complement value representing how far to shift the pixclk output pin relative to d out , in clk_in cycles. positive values shift pixclk later in time relative to d out (and thus relative to the internal array/datapath clock. no effect unless pixclk is divided by divide pixel clock. nn 7 x reserved 6:0 0x0000 divide pixel clock produces a pixclk that is divided by the value times two. the value must be zero or a power of 2. this will slow down the internal clock in the array control and datapath blocks, including pixel readout. it will not affect the a two-wire serial interface clock. a value of 0 corresponds to a pixclk with the same frequency as clk_in. a value of 1 means f_pixclk = (f_clk_in / 2); 2 means f_pixclk = (f_clk_in / 4); 64 means f_pixclk = (f_clk_in / 128); and so on. nn r11:0 r0x00b 15:0 0x0000 restart (r/w) 15:3 x reserved 2 0x0000 trigger setting this bit in snapshot mode will cause the next trigger to occur as if the trigger signal were properly asserted or de-asserted. ineffective if not in snapshot mode. the sense of this bit is not affected by invert trigger. when using this bit instead of the trigger signal, make sure that either the trigger signal is continuously asserted, or that the signal is continuously de-asserted and invert_trigger is set. nn 1 0x0000 pause restart when set, restart will not automatically be cleared. instead, the sensor will pause at row 0 after restart is set. when pause_restart is cleared, the sensor will resume. this allows for a repeatable delay from clearing restart to fv. nn 0 0x0000 restart setting this bit will cause the sensor to abandon the current frame and restart from the first row. it will take up to 2*t_row for the restart to take effect. this bit automatically resets to 0 unless pause_restart is set. nn table 7: core registers C register description (continued) register # dec hex bits default name frame sync'd bad frame pdf: 3846173010/source: 5724337828 aptina reserves the right to change products or specifications without notice. MT9M012_ds - rev.d 5/10 en 27 ?2007 aptina imaging corporation. all rights reserved. MT9M012: 1/4.5-inch 1.6mp cmos digital image sensor register descriptions advance r12:0 r0x00c 15:0 0x0000 shutter delay (r/w) y n a negative adjustment to the effective shutter width in aclks. see shutter_width_lower. r13:0 r0x00d 15:0 0x0000 reset (r/w) n n setting this bit will put the sensor into reset mode, which will set the sensor to its default power-up state and cause it to halt. clearing this bit will resume normal operation. this is equivalent to pulling the reset_bar pin low, except that the two-wire serial interface remains functional. r17:0 r0x011 15:0 0x3c04 pll config 1 (r/w) 15:8 0x003c pll m factor pll output frequency multiplier. nn 7:6 x reserved 5:0 0x0004 pll n divider pll output frequency divider minus 1. nn r30:0 r0x01e 15:0 0x0146 read mode 1 (r/w) 15:13 x reserved n n 12 0x0000 maintain frame rate when set, writing registers with the bf attribute will create bad frames, but if these writes would not otherwise change the frame rate, the frame rate will be maintained. when cleared, writing registers with the bf attribute will interrupt the frame rate to avoid creating a bad frame. nn 11 0x0000 xor line valid when set, produces a lv signal that is the xor of fv and the normal lv. ineffective if continuous line valid is set. when clear, produce a normal lv. nn 10 0x0000 continuous line valid when set, produce the lv signal even during the vertical blank period. when cleared, produces lv only when active rows are being read out (that is, only when fv is high). nn 9 0x0000 invert trigger when set, the sense of the trigger input signal will be inverted. nn 8 0x0001 snapshot when set, the sensor enters snapshot mode, and will wait for a trigger event between frames. when cleared, the sensor is in continuous mode. yn 7 0x0000 global reset when set, the global reset release shutter will be used. when cleared, the electronic rolling shutter will be used. yn table 7: core registers C register description (continued) register # dec hex bits default name frame sync'd bad frame pdf: 3846173010/source: 5724337828 aptina reserves the right to change products or specifications without notice. MT9M012_ds - rev.d 5/10 en 28 ?2007 aptina imaging corporation. all rights reserved. MT9M012: 1/4.5-inch 1.6mp cmos digital image sensor register descriptions advance r30:0 r0x01e 6 0x0001 bulb exposure when set, exposure time will be controlled by an external trigger. when cleared, exposure time will be controlled by the shutter_width_lower and shutter_width_upper registers. yn 5 0x0000 invert strobe when set, the strobe signal will be normally high, except during exposure, when it will be low. when clear, the strobe signal is normally low except during exposure. nn 4 0x0000 strobe enable when set, a strobe signal will be generated by the digital logic during integration. when clear, the strobe pin will be set to the value of invert_strobe. nn 3:2 0x0001 strobe start determines the timepoint when the strobe is asserted. 0: first trigger 1: simultaneous exposure 2: shutter width 3: second trigger yn 1:0 0x0002 strobe end determines the timepoint when the strobe is de-asserted. if this is set equal to or less than strobe_start, the width of the strobe pulse will be t_row. see strobe_start. yn r32:0 r0x020 15:0 0x0040 read mode 2 (r/w) 15 0x0000 mirror row when set, row readout in the active image occurs in reverse numerical order starting from (row_start + row_size). when clear, row readout of the active image occurs in numerical order. this has no effect on the readout of the dark rows. yy 14 0x0000 mirror column when set, column readout in the active image occurs in reverse numerical order, starting from (column_start + column_size). when clear, column readout of the active image occurs in numerical order. this has no effect on the readout of the dark columns. yn 13 x reserved 12 0x0000 show dark columns when set, the dark columns used for digital black level adjustment will be output to the left of the active image, making the output image wider. this has no effect on integration time or frame rate. when clear, only columns that are part of the active image will be output. yn 11 0x0000 show dark rows when set, the dark rows used for the analog black level adjustment will be output before the active image rows, making the output image taller. this has no effect on integration time or frame rate. when clear, only rows from the active image will be output. yn 10:7 x reserved table 7: core registers C register description (continued) register # dec hex bits default name frame sync'd bad frame pdf: 3846173010/source: 5724337828 aptina reserves the right to change products or specifications without notice. MT9M012_ds - rev.d 5/10 en 29 ?2007 aptina imaging corporation. all rights reserved. MT9M012: 1/4.5-inch 1.6mp cmos digital image sensor register descriptions advance r32:0 r0x020 6 0x0001 row blc when set, digitally compensates for differing black levels between rows by adding dark target (r73) and subtracting the average value of the 8 same- color dark pixels at the beginning of the row. when clear, digitally adds row black default offset (r75) to the value of each pixel. yn 5:0 x reserved r43:0 r0x02b 15:0 0x0010 green1 gain (r/w) 15 x reserved 14:8 0x0000 green1 digital gain digital gain for the green1 channel minus 1 times 8. the actual digital gain is (1 + value/8), and can range from 1 (a setting of 0) to 16 (a setting of 120) in increments of 1/8. yn 7x reserved 6 0x0000 green1 analog multiplier analog gain multiplier for the green1 channel minus 1. if 1, an additional analog gain of 2x will be applied. if 0, no additional gain is applied. yn 5:0 0x0010 green1 analogl gain analog gain setting for the green1 channel times 8. the effective gain for the channel is (((green1_digital_gain/8) + 1) * (green1_analog_multiplier + 1) * (green1_analog_gain/16)). yn r44:0 r0x02c 15:0 0x0010 blue gain (r/w) 15 x reserved 14:8 0x0000 blue digital gain digital gain for the blue channel minus 1 times 8. the actual digital gain is (1 + value/8), and can range from 1 (a setting of 0) to 16 (a setting of 120) in increments of 1/8. yn 7 x reserved 6 0x0000 blue analog multiplier analog gain multiplier for the blue channel minus 1. if 1, an additional analog gain of 2x will be applied. if0, no additional gain is applied. yn 5:0 0x0010 blue analog gain analog gain setting for the blue channel times 8. the effective gain for the channel is (((blue_digital_gain/8) + 1) * (blue_analog_multiplier + 1) * (blue_analog_gain/16)). yn table 7: core registers C register description (continued) register # dec hex bits default name frame sync'd bad frame pdf: 3846173010/source: 5724337828 aptina reserves the right to change products or specifications without notice. MT9M012_ds - rev.d 5/10 en 30 ?2007 aptina imaging corporation. all rights reserved. MT9M012: 1/4.5-inch 1.6mp cmos digital image sensor register descriptions advance r45:0 r0x02d 15:0 0x0010 red gain (r/w) 15 x reserved 14:8 0x0000 red digital gain digital gain for the red channel minus 1 times 8. the actual digital gain is (1 + value/8), and can range from 1 (a setting of 0) to 16 (a setting of 120) in increments of 1/8. yn 7 x reserved 6 0x0000 red analog multiplier analog gain multiplier for the red channel minus 1. if 1, an additional analog gain of 2x will be applied. if 0, no additional gain is applied. yn 5:0 0x0010 red analog gain analog gain setting for the red channel times 8. the effective gain for the channel is (((red_digital_gain/8) + 1) * (red_analog_multiplier + 1) * (red_analog_gain/16)). yn r46:0 r0x02e 15:0 0x0010 green2 gain (r/w) 15 x reserved 14:8 0x0000 green2 digital gain digital gain for the green2 channel minus 1 times 8. the actual digital gain is (1 + value/8), and can range from 1 (a setting of 0) to 16 (a setting of 120) in increments of 1/8. yn 7 x reserved 6 0x0000 green2 analog multiplier analog gain multiplier for the green2 channel minus 1. if 1, an additional analog gain of 2x will be applied. if 0, no additional gain is applied. yn 5:0 0x0010 green2 analog gain analog gain setting for the green2 channel times 8. the effective gain for the channel is (((green2_digital_gain/8) + 1) * (green2_analog_multiplier + 1) * (green2_analog_gain/16)). yn r53:0 r0x035 15:0 0x0010 global gain (wo) y n writing the global_gain sets all four individual gain registers r43Cr46 to the value. this register should not be read. see green1_gain (r43) for a description of the various fields. r73:0 r0x049 15:0 0x00a8 row black target (r/w) y n the target black level for the row blc algorithm. r75:0 r0x04b 15:0 0x0028 row black default offset (r/w) y n a two's complement offset digitally added to all active image pixel values when row blc (r30[6]) is disabled. r91:0 r0x05b 15:0 0x0001 blc_sample_size (r/w) n n if set, the "moving average" calculation in the blc algorithm will use a sample size of 32. if cleared, it will use a sample size of 1 (that is, each frame's black level will be considered independent of other frames). table 7: core registers C register description (continued) register # dec hex bits default name frame sync'd bad frame pdf: 3846173010/source: 5724337828 aptina reserves the right to change products or specifications without notice. MT9M012_ds - rev.d 5/10 en 31 ?2007 aptina imaging corporation. all rights reserved. MT9M012: 1/4.5-inch 1.6mp cmos digital image sensor register descriptions advance r92:0 r0x05c 15:0 0x005a blc_tune_1 (r/w) 15:12 x reserved 11:8 0x0000 blc_delta_damping a number subtracted from the calculated correction's magnitude when in delta mode. setting this to a positive number will correct by that much less than the delta value. a negative (two's complement) number will correct by more (possibly worsening the overshoot). this applies to the magnitude of the delta, so a positive damping value will be subtracted from a positive delta and added to a negative delta. yn 7:0 0x005a blc_dac_settling_time the number of pixclks it takes for a newly set offset to take effect divided by 2. used to configure the fast sample algorithm. after setting a calibration value in fast sample mode, (value * 2) pixclks will elapse before the next sample is taken. yn r93:0 r0x05d 15:0 0x2d13 blc_delta_thresholds (r/w) 15 x reserved 14:8 0x002d blc_high_delta_threshold upper delta threshold divided by 4. if the average black value for a color is higher than this value times 4 or lower than blc_low_delta_threshold times 4, the fast sampling and binary search modes will be activated (if enabled). once the black level is between the blc_high_delta_threshold and the blc_low_delta_threshold, the delta adjustment mode will be used (though fast sample mode will continue until the end of the frame). this value should be set no lower than blc high target threshold. yn 7 x reserved 6:0 0x0013 blc_low_delta_threshold lower delta threshold divided by 4. see blc_high_delta_threshold. should be no higher than blc_low_target_threshold. yn r94:0 r0x05e 15:0 0x41ff blc_tune_2 (r/w) 15 x reserved 14:12 0x0004 blc_step_size base 2 log of the change in pixel value (in lsbs) of a pixel when the analog offset is changed by one. nn 11:9 x reserved 8:0 0x01ff blc_max_adjust the maximum adjustment (positive or negative) that the blc delta adjustment mode is allowed to make to the analog offset. nn table 7: core registers C register description (continued) register # dec hex bits default name frame sync'd bad frame pdf: 3846173010/source: 5724337828 aptina reserves the right to change products or specifications without notice. MT9M012_ds - rev.d 5/10 en 32 ?2007 aptina imaging corporation. all rights reserved. MT9M012: 1/4.5-inch 1.6mp cmos digital image sensor register descriptions advance r95:0 r0x05f 15:0 0x231d blc_target_thresholds (r/w) 15 x reserved 14:8 0x0023 blc_high_target_threshold the upper target threshold of the blc algorithm divided by 4. the target black value is 4 times the average of the blc_high_target_threshold and the blc_low_target_threshold. when the black value for a color is within these thresholds, it will be considered to be on target. yn 7 x reserved 6:0 0x001d blc_low_target_threshold the lower target threshold for the blc algorithm divided by 4. see blc high target threshold above. yn r96:0 r0x060 15:0 0x0020 green1_offset (r/w) y n two's complement representation of the analog offset value for green1. if manual_blc (r98[0]) is set, this value will be used as the analog offset. otherwise, the value may be overridden by the blc algorithm. when read, this register returns the offset currently in use. the user-programmed value is always retained internally, and may be read by setting manual_blc. a value of C256 w ill set the offset to C255. r97:0 r0x061 15:0 0x0020 green2_offset (r/w) y n two's complement representation of the analog offset value for green2. see green1_offset. table 7: core registers C register description (continued) register # dec hex bits default name frame sync'd bad frame pdf: 3846173010/source: 5724337828 aptina reserves the right to change products or specifications without notice. MT9M012_ds - rev.d 5/10 en 33 ?2007 aptina imaging corporation. all rights reserved. MT9M012: 1/4.5-inch 1.6mp cmos digital image sensor register descriptions advance r98:0 r0x062 15:0 0x0000 black_level_calibration (r/w) 15 0x0000 disable_fast_sample when set, the fast sampling mode (multiple samples per frame) will not be used if the black level falls outside the delta thresholds; instead, only one sample-adjust will take place per frame. binary search mode may still be used. when cleared, fast sample mode will be used when necessary. yn 14 0x0000 lock_green_calibration when set, the calibration offset chosen for green1 will be used for green2 pixels as well. only effective if green1_analog_gain equals green2_analog_gain and green1_analog_multiplier equals green2_analog_multiplier. yn 13 0x0000 lock_red_blue_calibration when set, the calibration offset chosen for red will be used for blue pixels as well. only effective if red_analog_gain equals blue_analog_gain and red_analog_multiplier equals blue_analog_multiplier. yn 12 0x0000 recalculate_black_level when set, any running averages w ill be reset and the fast sample and binary search modes will be activated (if enabled). this bit always reads 0. yn 11 0x0000 disable_binary_search when set, binary search mode will not be used when the black level falls outside the delta thresholds; instead the delta mode will be used. fast sampling mode may still be used if enabled. yn 10:2 x reserved 1 0x0000 disable_calibration when set, analog calibration is disabled. when cleared, the programmed or automatic offsets will be used. nn 0 0x0000 manual_blc when set, the user-programmed calibration offsets from r96-r97 and r99Cr100 w ill be used. also, black level calculation will be disabled. when cleared, the blc algorithm will adjust the offsets to maintain the target black level. yn r99:0 r0x063 15:0 0x0020 red_offset (r/w) y n two's complement representation of the analog offset value for red. see green1_offset. r100:0 r0x064 15:0 0x0020 blue_offset (r/w) y n two's complement representation of the analog offset value for blue. see green1_offset. r148:0 r0x094 15:0 0x290e reserved 15:14 x reserved 13:8 0x0029 reserved 7:1 0x0007 reserved 0 0x0000 reserved n n r157:0 r0x09d 15:0 0x2255 formatter0 (r/w) 15:12 0x0002 fv delay adjustment frame valid delay control (twos complement [-8, 7]). yn table 7: core registers C register description (continued) register # dec hex bits default name frame sync'd bad frame pdf: 3846173010/source: 5724337828 aptina reserves the right to change products or specifications without notice. MT9M012_ds - rev.d 5/10 en 34 ?2007 aptina imaging corporation. all rights reserved. MT9M012: 1/4.5-inch 1.6mp cmos digital image sensor register descriptions advance 11:8 0x0002 lv delay adjustment line valid delay control (twos complement [-8, 7]). yn r159:0 r0x09f 15:0 0x0071 formatter2 (r/w) 13 0x0000 pixclk output enable pixclk output enable 0 : pixclk is always set 0 {default} 1 : enable nn 12 0x0000 d out output enable parallel data output enable 1 : enable, 0 : d out bus is always set 0x000 {default} nn r255:0 r0x0ff 15:0 0x1402 chip_version_alt (ro) n n mirror of r0[15:0]. table 7: core registers C register description (continued) register # dec hex bits default name frame sync'd bad frame pdf: 3846173010/source: 5724337828 aptina reserves the right to change products or specifications without notice. MT9M012_ds - rev.d 5/10 en 35 ?2007 aptina imaging corporation. all rights reserved. MT9M012: 1/4.5-inch 1.6mp cmos digital image sensor signal chain and datapath advance signal chain and datapath the signal chain and datapath are shown in figure 13. each color is processed indepen- dently, including separate gain and offset settings. voltages sampled from the pixel array are first passed through an analog gain stag e, which can produce gain factors between 1 and 7.875. an analog offset is then applied, and the signal is sent through a 12-bit analog-to-digital converter. in the digital space, a digital gain factor of between 1 and 16 is applied, and then a digital offset of betw een ?2048 and 2047 is added. the resulting 12- bit pixel value is then output on the d out [11:0] ports. the analog offset applied is determined au tomatically by the black level calibration algorithm, which attempts to shift the output of the analog signal chain so that black is maintained. the digital offset is a fine-tuning of the analog offset. figure 13: signal path gains the MT9M012 supports two types of gain: anal og gain and digital gain. combined, gains of between 1 and 126 are possible. it is reco mmended that analog gain should be maxi- mized before applying digital gain. the sensor provides per-color gain control as well as the option of global gain control. per-color and global gain control can be used interchangeably. a write to a global gain register is aliased as a write of the same data to the four associated color-dependent gain registers. the combined gain for a color c is given by: g c = ag c x dg c (eq 1) analog gain the analog gain is specified independently for each color channel. there are two components, the gain and the multiplier. the gain is specified by green1_analog_gain, red_analog_gain, blue_analog_gain, and gr een2_analog_gain. the analog multiplier is specified by green1_analog_multiplier, red_analog_multiplier, blue_analog_multiplier, and green2_analog_m ultiplier. these combine to form the analog gain for a given color c, as shown in this equation: ag c = (1 + c_analog_multiplier) (c_analog_gain / 16) (eq 2) the gain component can range from 0 to 7.875 in steps 0.0625 for < 4 gain, and 0.125 for > 4 gain, and the multiplier component can be either 0 or 1 (resulting in a multiplier of 1 or 2). however, it is best to keep the gain component between 1 and 4 for the best noise performance, and use the multiplier for gains between 4 and 7.825. pixel voltage digital gain analog gain digital datapath x + analog signal chain x + digital offset correction black level calibration d out [11: 0] adc analog offset pdf: 3846173010/source: 5724337828 aptina reserves the right to change products or specifications without notice. MT9M012_ds - rev.d 5/10 en 36 ?2007 aptina imaging corporation. all rights reserved. MT9M012: 1/4.5-inch 1.6mp cmos digital image sensor signal chain and datapath advance digital gain the digital gain is specified independently for each color channel in steps of 0.125. it is controlled by the register fields gr een1_digital_gain, red_digital_gain, blue_digital_gain, and green2_digital_gain. the digital gain for a color c is given by: dg c = 1 + (c_digital_gain / 8) (eq 3) offset the MT9M012 sensor can apply an offset or shift to the image data in several ways. an analog offset can be applied on a color-wise basis to the pixel voltage as it enters the adc. this makes it possible to adjust for offset introduced in the pixel sampling and gain stages to be removed, centering the resu lting voltage swing in the adc's range. this offset can be automatically determined by the sensor using the automatic black level calibration (blc) circuit, or it can be set manual ly by the user. it is a fairly coarse adjust- ment, with adjustment step sizes of four to eight lsbs. digital offset is also added on a color-wise and line-wise basis to fine-tune the black level of the output image. this offset is based on an average black level taken from each row's dark columns, and is automatically determined by the digital row-wise black level cali- bration (rblc) circuit. if the rblc circuit is not used, a user-defined offset can be applied instead. this offset has a resolution of 1 lsb. a digital offset is added on a color-wise basis to account for channel offsets that can be introduced due to ?even? and ?odd? pixels of the same color going through a slightly different adc chain. this offset is automatically determined based on dark row data, but it can also be manually set. analog black level calibration the MT9M012 black level calibration circuitry provides a feedback control system since adjustments to the analog offset are imprecise by nature. the goal is that within the dark row region of any supported output image si ze, the offset should have been adjusted such that the average black level falls within the specified target thresholds. the analog offsets normally need a major ad justment only when leaving the reset state or when there has been a change to a color' s analog gain. factors like shutter width and temperature have lower-order impact, and generally only require a minor adjustment to the analog offsets. the MT9M012 has various calibration modes to keep the system stable while still supporting the need for rapid offset adjustments when necessary. digital black level calibration digital black level calibration is the final calc ulation applied to pixel data before it is output. it provides a precise black level to complement the coarser-grained analog black level calibration, and also corrects for black level shift introduced by digital gain. this correction applies to the active columns for all rows, including dark rows. pdf: 3846173010/source: 5724337828 aptina reserves the right to change products or specifications without notice. MT9M012_ds - rev.d 5/10 en 37 ?2007 aptina imaging corporation. all rights reserved. MT9M012: 1/4.5-inch 1.6mp cmos digital image sensor features advance features pll-generated master clock the pll can generate a pixclk clock signal whose frequency is up to 49.5 mhz (input clock from 8?18 mhz). the pll-generated cloc k can be controlled by programming the appropriate register. it is possible to bypass the pll and use extclk as master clock. by default, the pll is powered up. the pll contains a prescaler to divide th e input clock applied on extclk, a vco to multiply the prescaler output, and pll output divider stage to generate the output clock. the clocking structure is shown in figure 14. pll control can be programmed to generate desired pi xel clock frequency. figure 14: pll-generated master clock note: the pll control registers must be programm ed while the sensor is in the software standby state. the effect of programming the pll divisors while the sensor is in the streaming state is undefined. pll setup to use the pll: 1. bring the MT9M012 up as normal, ensure that f extclk is between 8 and 18 mhz. 2. initialize the pll with th e following register settings: 2a. r0x10 = 0x0051 2b. r0x10 = 0x0050 2c. r0x10 = 0x0051 3. set pll_m_factor and pll_n_divider based on the desired input ( f extclk) and out- put ( f pixclk) frequencies. using this formula: f pixclk = f vco/6 where f vco = ( f extclk x m) / n m = pll_m_factor, n = (pll_n_divider + 1) default condition: f extclk = 18 mhz pll_m_factor = 0x3c (60), pll_n_divider = 0x4 f pixclk = 36 mhz 4. wait 1ms to ensure that the vco has locked. extclk pll output clock pll_n_d ivider +1 pre pll div (pfd) pll input clock pll multiplier (vco) pll output div pll_out_divider(6) pll_m_factor sysclk (pixclk) n m pdf: 3846173010/source: 5724337828 aptina reserves the right to change products or specifications without notice. MT9M012_ds - rev.d 5/10 en 38 ?2007 aptina imaging corporation. all rights reserved. MT9M012: 1/4.5-inch 1.6mp cmos digital image sensor features advance maintaining a constant frame rate maintaining a constant frame rate while contin uing to have the ability to adjust certain parameters is often desired. this is not alwa ys possible, however, since register updates are synchronized to the read pointer, and the shutter pointer for a frame is usually active during the readout of the previous frame. therefore, any register changes that could affect the row time or the set of rows sample d causes the shutter pointer to start over at the beginning of the next frame. by default, the following register fields caus e a ?bubble? in the output rate (the vertical blank increases for one frame) if they are written in continuous mode, even if the new value would not change the resulting frame rate: ? row_start ?row_size ?column_size ?horizontal_blank ?vertical_blank ? shutter_delay ? mirror_row the size of this bubble is (sw t row), calculating the row time according to the new settings. the shutter_width_lower and shutter_widt h_upper fields may be written without causing a bubble in the output rate unde r certain circumstances. since the shutter sequence for the next frame often is active du ring the output of the current frame, this would not be possible without special provisio ns in the hardware. writes to these regis- ters take effect two frames after the frame they are written, which allows the shutter width to increase without interrupting the ou tput or producing a corrupt frame (as long as the change in shutter width does not affect the frame time). synchronizing register writ es to frame boundaries changes to most register fields that affect th e size or brightness of an image take effect on the frame after the one during which they are written. these fields are noted as ?synchronized to frame boundaries? in table 6 on page 19. to ensure that a register update takes effect on the next frame, the write operation must be completed after the leading edge of fv and before the trailing edge of fv. as a special case, in snapshot modes (see belo w), register writes that occur after fv but before the next trigger will take effect imme diately on the next frame, as if there had been a restart. however, if the trigger for the next frame in ers snapshot mode occurs during fv, register writes take effect as with continuous mode. table 8: frequency parameters parameter equation min max unit pll_n_divider C 0 8 pll_m_factor C 16 180 f extclk C 8 18 mhz f pfd f extclk /(pll_n_divider+1) 2 18 mhz f vco f extclk * pll_m_factor/(pll_n_divider+1) 240 360 mhz pdf: 3846173010/source: 5724337828 aptina reserves the right to change products or specifications without notice. MT9M012_ds - rev.d 5/10 en 39 ?2007 aptina imaging corporation. all rights reserved. MT9M012: 1/4.5-inch 1.6mp cmos digital image sensor features advance additional control over the timing of register updates can be achieved by using synchronize_changes. if this bit is set, writes to certain register fields that affect the brightness of the output image do not take effect immediately. instead, the new value is remembered internally. when synchronize_ch anges is cleared, all the updates simulta- neously take effect on the next frame (as if they had all been written the instant synchronize_changes was cleared). register fields affected by this bit are identified in table 7: core registers ? register description on page 24. fields not identified as being frame-synchronized or affected by synchronize_changes are updated immediately after the register writ e is completed. the effect of these regis- ters on the next frame can be difficult to predict if they affect the shutter pointer. restart to restart the MT9M012 at any time during the operation of the sensor, write a ?1? to the restart register (r0x0b[0] = 1). this has two e ffects: first, the current frame is interrupted immediately. second, any writes to frame-synchronized registers and the shutter width registers take effect immediately, and a new frame starts (in continuous mode). register updates being held by synchronize_changes do not take effect until that bit is cleared. the current row and one following row complete before the new frame is started, so the time between issuing the rest art and the beginning of the next frame can vary by about t row. if pause_restart is set, rather than immedi ately beginning the next frame after a restart in continuous mode, the sensor pauses at the beginning of the next frame until pause_restart is cleared. this can be used to achieve a deterministic time period from clearing the pause_restart bit to the beginni ng of the first frame, meaning that the controller does not need to be tightly synchronized to lv or fv. note: when pause_restart is cleared, be sure to le ave restart set to ?1? for proper operation. the restart bit will be cleared automatically by the device. window size the output image window of the pixel array (the fov) is programmable and defined by four register fields. column_start and row_start define the x and y coordinates of the upper left corner of the fov. column_size defines the width of the fov, and row_size defines the height of the fov in array pixels. the column_start and row_start fields must be set to an even number. the column_size and row_size fields must be set to odd numbers (resulting in an even size for the fov). the row_start register should be set no lower than 12 if either manual_blc is cleared or show_dark_rows is set. the width of the output image, w, is column_size + 1 and height, h, is row_size + 1 . in default, a full resolution image size of 1440 x 1080 in output. pdf: 3846173010/source: 5724337828 aptina reserves the right to change products or specifications without notice. MT9M012_ds - rev.d 5/10 en 40 ?2007 aptina imaging corporation. all rights reserved. MT9M012: 1/4.5-inch 1.6mp cmos digital image sensor features advance readout modes the MT9M012 sensor supports mirror readout mode. image can be flipped in the vertical and/or mirrored in the horizontal directions. mirror mode by default, active pixels in an image are output in row-major order (an entire row is output before the next row is begun), from lowest row/column number to highest. mirror mode allows the output order of the rows and columns to be reversed. this only affects pixels in the active region of the image, not pixels read out as dark rows or dark columns. when the readout direction is reversed, the color order is reversed as well (for example, red, green, red, and so on instead of green, red, green, and so on), thus causing the bayer order of the output image to change. column mirror the readout order of the columns are reversed, as shown in figure 15. figure 15: six pixels in normal and column mirror readout modes row mirror the readout order of the rows are reversed, as shown in figure 16. figure 16: six rows in normal and row mirror readout modes d out [11:0] line_valid normal readout g0 (11:0) r0 (11:0) g1 (11:0) r1 (11:0) g2 (11:0) r2 (11:0) d out [11:0] reversed readout g2 (11:0) r1 (11:0) g1 (11:0) r0 (11:0) g0 (11:0) r2 (11:0) d out [11:0] frame_valid normal readout row0 row1 row2 row3 row4 row5 d out [11:0] reverse readout row0 row1 row2 row3 row4 row5 pdf: 3846173010/source: 5724337828 aptina reserves the right to change products or specifications without notice. MT9M012_ds - rev.d 5/10 en 41 ?2007 aptina imaging corporation. all rights reserved. MT9M012: 1/4.5-inch 1.6mp cmos digital image sensor features advance image acquisition modes the MT9M012 supports two image acquisition modes (shutter types), electronic rolling shutter (ers), and global reset release (grr). electronic rolling shutter the ers modes take pictures by scanning the rows of the sensor. on the first scan, each row is released from reset, starting the exposure. on the second scan, the row is sampled, processed, and returned to the reset state. the exposure for any row is therefore the time between the first and second scans. each ro w is exposed for the same duration, but at slightly different point in time, which can cause a shear in moving subjects. whenever the mode is changed to an ers mode (even from another ers mode), and before the first frame following reset, there is an anti-blooming sequence where all rows are placed in reset. this sequence must complete before continuous readout begins. this delay is: t allreset = 16 1096 t aclk (where t aclk is 2 * t pixclk) (eq 4) global reset release the grr modes attempt to address the shearing effect by starting exposures of all rows at the same time. instead of the first scan used in ers mode, the reset to each row is released simultaneously. the second scan oc curs as normal, so th e exposure time for each row would different. typically, an external mechanical shutter would be used to stop the exposure of all rows simultaneously. in grr modes, there is a startup overhead be fore each frame as all rows are initially placed in the reset state ( t allreset). unlike ers mode, this delay always occurs before each frame. however, it occurs as soon as possible after the preceding frame, so typically the time from trigger to the start of exposure does not include this delay. to ensure that this is the case, the first trigger must occur no sooner than t allreset after the previous frame is read out. exposure the nominal exposure time, t exp, is the effective shutter time in ers modes, and is defined by the shutter width (sw), and the shutter overhead (so), which includes the effect of shutter_delay. exposure time for other modes is defined relative to this time. increasing shutter_delay (sd) decreases the exposure time. exposure times are typically specified in units of row time, although it is possible to fine-tune exposures in units of t aclks (where t aclk is 2* t pixclk). this is expressed in the formula: t exp = sw t row ? so 2 t pixclk (eq 5) the exposure time is calculated by determin ing the reset time of each pixel row (with time 0 being the start of the first row time), and subtracting it from the sample time. under normal conditions in ers modes, ever y pixel should end up with the same expo- sure time. in global shutter release modes, the exposure times of individual pixels can vary. pdf: 3846173010/source: 5724337828 aptina reserves the right to change products or specifications without notice. MT9M012_ds - rev.d 5/10 en 42 ?2007 aptina imaging corporation. all rights reserved. MT9M012: 1/4.5-inch 1.6mp cmos digital image sensor features advance in global shutter release modes (described later), exposure time starts simultaneously for all rows, but still ends as defined above. in a real system, the exposure would be stopped by a mechanical shutter, which would effectively stop the exposure to all rows simultaneously. since this specification does not consider the effect of an external shutter, each output row's exposure time will differ by t row from the previous row. global shutter modes also introduce a constant added to the shutter time for each row, since the exposure starts during the global shutter sequence, and not during any row's shutter sequence. in bulb_exposure modes (also detailed later), the exposure time is determined by the width of the trigger pulse rather than the sh utter width registers. in ers bulb mode, it will still be a multiple of row times, and the shutter overhead equation still applies. in grr bulb mode, the exposure time is granular to aclks, and shutter overhead (and thus shutter_delay) have no effect. operating modes in the default operating mode, the MT9M012 continuously samples and outputs frames. it can be put in snapshot or triggered mode by setting snapshot, which means that it samples and outputs a frame only when triggered. to leave snapshot mode, it is neces- sary to first clear snapshot then issue a restart. when in snapshot mode, the sensor can use the ers or the grr. the exposure can be controlled as normal, with the shutter_width_lower and shutter_width_upper regis- ters, or it can be controlled using the external trigger signal. the various operating modes are summarized in table 9. notes: 1. in ers bulb mode, sw must be greater than 4 (use trigger wider than t row*4). all operating modes share a common set of operations: 1. wait for the first trigger, then start the exposure. 2. wait for the second trigger, then start the readout. the first trigger is by default automatic, prod ucing continuous images. if snapshot is set, the first trigger can either be a low level on the trigger pin or writing a ?1? to the trigger register field. if invert_trigger is set, the first trigger is a high level on trigger pin (or a ?1? written to trigger register field) . since trigger is level-sensitive, multiple frames can be output (with a frame rate of t frame) by holding trigger pin at the trig- gering level. table 9: operating modes mode settings description ers continuous default frames are output continuously at the frame rate defined by t frame. ers is used, and the exposure time is electronically controlled to be t exp. ers snapshot snapshot = 1 frames are output one at a time, with each frame initiated by a trigger. ers is used, and the exposure time is electronically controlled to be t exp. ers bulb snapshot = 1; bulb_exposure = 1 frames are output one at a time, with each frame's exposure initiated by a trigger. ers is used. end of exposure and readout are initiated by a second trigger. grr snapshot snapshot = 1; global_reset = 1 frames are output one at a time, with each frame initiated by a trigger. grr is used. readout is electronically triggered based on sw. grr bulb snapshot = 1; bulb_exposure = 1; global_reset = 1 frames are output one at a time, with each frame initiated by a trigger. grr is used. readout is initiated by a second trigger. pdf: 3846173010/source: 5724337828 aptina reserves the right to change products or specifications without notice. MT9M012_ds - rev.d 5/10 en 43 ?2007 aptina imaging corporation. all rights reserved. MT9M012: 1/4.5-inch 1.6mp cmos digital image sensor features advance the second trigger is also normally automatic, and generally occurs sw row times after the exposure is started. if bulb_exposure is set, the second trigger can either be a high level on trigger or a write to restart. if invert_trigger is set, the second trigger is a low level on trigger (or a restart). in bulb modes, the minimum possible exposure time depends on the mechanical shutter used. after one frame has been output, the chip will reset back to step 1 above, eventually waiting for the first trigger again. the next trigger may be issued after ((vb - 8) x t row ) in ers modes or t allrest in grr modes. the choice of shutter type is made by global_reset. if it is set, the grr shutter is used; otherwise, ers is used. the two shutters are described in ?electronic rolling shutter? on page 41 and ?global reset release? on page 41. the default ers continuous mode is shown in figure 3 on page 10. figure 17 shows default signal timing for ers snapshot mode s, while figure 18 on page 44 shows default signal timing for grr snapshot modes. figure 17: ers snapshot timing trigger strobe frame_valid line_valid d out trigger strobe frame_valid line_valid d out (a) ers snapshot (b) ers bulb tt1 tse tsw tt2 (h + vb) x t row (h + vb) x t row 8 x t row t row t row 8 x t row t row 8 x t row t row sw x t row 8 x t row first row exposure second row exposure first row exposure second row exposure sw x t row tt1 tsw tt2 tse pdf: 3846173010/source: 5724337828 aptina reserves the right to change products or specifications without notice. MT9M012_ds - rev.d 5/10 en 44 ?2007 aptina imaging corporation. all rights reserved. MT9M012: 1/4.5-inch 1.6mp cmos digital image sensor features advance figure 18: grr snapshot timing strobe control to support synchronization of the exposure with external events such as a flash or mechanical shutter, the MT9M012 produces a st robe output. by default, this signal is asserted for approximately the time that all rows are simultaneously exposing, minus the vertical blank time, as shown in figure 17 on page 43 and figure 18. also indicated in these figures are the leading and trailing edges of strobe, which an be configured to occur at one of several timepoints. the lead ing edge of strobe occurs at strobe_start, and the trailing edge at strobe_end, whic h are set to codes described in table 10. if strobe_start and strobe_end are set to the same timepoint, the strobe is a t row wide pulse starting at the strobe_start ti mepoint. if the settings are such that the strobe would occur after the trailing edge of fv, the strobe may be only t aclk wide; however, since there is no concept of a row at that time. the sense of the strobe signal can be inverted by setting invert_strobe (r0x1e [5] = 1). to use strobe as a flash in snap- shot modes or with mechanical shutter, set the strobe_enable register bit field (r0x1e[4] = 1). table 10: strobe timepoints symbol timepoint code tt1 trigger 1 (start of shutter scan) C tse start of exposure (all rows simultaneously exposing) offset by vb 1 tsw end of shutter width (expiration of the internal shutter width counter) 2 tt2 trigger 2 (start of readout scan) 3 trigger strobe frame_valid line_valid d out trigger strobe frame_valid line_valid d out (a) grr snapshot (b) grr bulb tse tsw tt2 tsw tse tt2 vb x t row + 2000 x t aclk t row 8 x t row t row 8 x t row first row exposure first row exposure vb x t row + 2000 x t aclk second row exposure second row exposure sw x t row + 2000 x t aclk sw x t row + 2000 x t aclk tt1 tt1 pdf: 3846173010/source: 5724337828 aptina reserves the right to change products or specifications without notice. MT9M012_ds - rev. d 5/10 en 45 ?2007 aptina imaging corporation. all rights reserved. MT9M012: 1/4.5-inch 1.6mp cmos digital image sensor timing specifications aptina confidential and proprietary advance timing specifications power-up sequence use the following sequence when powering up the MT9M012: 1. ensure reset_bar is asserted (driven low). 2. bring up all the power supplies at the same time. if both the analog and the digital supplies cannot be brought up simultaneously, ensure the digital supply comes up first. ensure that all power rails reach minimum voltages. 3. de-assert reset_bar (driven high ) to make the sensor active. figure 19: power supply power-up sequence notes: 1. the lv signal must be connected to an external pull-down resistor (typically from 10kC100k ). 2. the dotted lines are drawn in reference to the minimum voltage of the power supply or minimum vih for reset_bar. please refer table 17 on page 52 for dc electrical specifications. 3. after all power rails reach their minimum voltage value, reset_bar should stay at low at least one mil- lisecond. at least one stable extclk input is required before reset_bar is released. power-down sequence follow this sequence to power down the sensor. see figure 20 for detailed timing. 1. assert reset_bar (driven low). table 11: power supply power-up timing symbol parameter min typ max units t 1v dd _io to v dd 0C500 ms t 2v dd to v dd _pll 0 C 500 t 3v dd _pll to v aa , vaa_pix 0 C 500 t 4 reset activation 1 C C v dd _ io v dd v dd _ pll v aa , v aa _pix extclk reset_bar 2.8v 1.8v 2.8v 2.8v power up t 3 t 4 t2 t 1 pdf: 3846173010/source: 5724337828 aptina reserves the right to change products or specifications without notice. MT9M012_ds - rev. d 5/10 en 46 ?2007 aptina imaging corporation. all rights reserved. MT9M012: 1/4.5-inch 1.6mp cmos digital image sensor timing specifications aptina confidential and proprietary advance 2. remove all power supplies simultaneously or at least within th e timing parameters specified in table 12. figure 20: power supply power-down sequence power-up initial commands 1. after power-up, initialize the pll as follows: r0x010 = 0x0051 r0x010 = 0x0050 r0x010 = 0x0051 r0x011 = mmnn // pll values if necessary r0x010 = 0x0053 2. wait 1?2 ms for pll to lock. 3. do the rest of sensor initialization sequence per ?power-up sequence? on page 45. table 12: power supply power-down timing symbol parameter min typ max units t 1v aa , vaa_pix to v dd _pll 0 C 500 ms t 2v dd _pll to v dd 0C500 t 3v dd to v dd _io 0 C 500 t 4 reset activation 1 C C v aa, vaa_pix v dd _ pll v dd v dd_ io extclk reset_bar 2.8v 2.8v 1.8v 2.8v power down t 3 t 4 t 2 t 1 pdf: 3846173010/source: 5724337828 aptina reserves the right to change products or specifications without notice. MT9M012_ds - rev. d 5/10 en 47 ?2007 aptina imaging corporation. all rights reserved. MT9M012: 1/4.5-inch 1.6mp cmos digital image sensor timing specifications aptina confidential and proprietary advance reset two types of reset are available: 1. a hard reset is issued by toggling reset_bar. 2. a soft reset is issued by writing commands through the serial interface. hard reset assert (low) reset_bar and apply at least on e extclk pulse. all registers return to the factory defaults. when the signal is de-asserted (high), the chip resumes normal operation. soft reset a soft reset to the sensor has the same affect as the hard reset and can be activated by setting the register field to ?1?: r0x0d[0] = 1. all registers except the following will be reset: ?chip_enable ? synchronize_changes ?reset ? pll_m_factor ? pll_n_divider when the field is returned to ?0,? the chip resumes normal operation. signal state during reset table 13 shows the state of the signal in terface during reset (when reset_bar is asserted) and during standby (after exit from reset and before any registers within the sensor have been changed from their default power-up values). table 13: signal state during reset signal name signal type reset signal state sclk input input reset_bar input input extclk input input trigger input input test input input s data i/o input strobe output tri-state d out [11:0] output output pixclk output high fv input input lv input input pdf: 3846173010/source: 5724337828 aptina reserves the right to change products or specifications without notice. MT9M012_ds - rev. d 5/10 en 48 ?2007 aptina imaging corporation. all rights reserved. MT9M012: 1/4.5-inch 1.6mp cmos digital image sensor timing specifications aptina confidential and proprietary advance standby and chip enable (power save mode) the MT9M012 can be put in a low-power standby state from streaming state by programming r0x07[1]. two standby mode s (stby_a and stby_b ) are selectable through r0x10[13:12]. conditions are shown in table 14. when the sensor is put in standby, all internal clocks are gated, and anal og circuitry is put in a state that it draws minimal power. the two-wire serial interface remains minima lly active so that the chip_enable bit can subsequently be cleared. reads cannot be performed and only the chip_enable register is writable. if the sensor was in continuous mode when put in standby, it resumes from where it was when standby was deactivated. for maximum power savings in standby mode, extclk should not be toggling. when standby mode is entered, the pll is disabled automati- cally or powered down. it must be manually re-enabled when leaving standby as needed. note: stby_b is for master mode in the system, which keeps to output sync (fv / lv) sig- nals. stby_a is for both modes. to enter standby stby_a: set r0x027[7] = 1 set r0x094[0] = 1 set r0x00b = 0x0003 set r0x007[1] = 0 to enter standby stby_b: set r0x00a[12:13] = 1 to leave standby stby_a: set r0x027[7] = 0 set r0x094[0] = 0 set r0x00b = 0x0000 set r0x007[1] = 1 set r0x010[1] = 0 set r0x010[1] = 1 to leave standby stby_b: set r0x00a[12:13] = 0 notes: 1. the execution of standby will take place after the completion of the current line by default. table 14: standby modes circuit type stby_a stby_b analog core disable disable digital data pass array control disable enable digital ac disable enable digital clk gen (gated clock ctrl) enable (master clock bypass) enable pll disable enable pdf: 3846173010/source: 5724337828 aptina reserves the right to change products or specifications without notice. MT9M012_ds - rev. d 5/10 en 49 ?2007 aptina imaging corporation. all rights reserved. MT9M012: 1/4.5-inch 1.6mp cmos digital image sensor spectral characteristics advance spectral characteristics figure 21: typical color spectral characteristics figure 22: chief ray angle (cra) vs. image height cra vs. image height plot image height cra (%) (mm) (deg) 000 5 0.099 2.39 10 0.198 4.76 15 0.297 7.09 20 0.396 9.38 25 0.495 11.65 30 0.594 13.84 35 0.693 15.91 40 0.792 17.86 45 0.891 19.67 50 0.990 21.32 55 1.089 22.75 60 1.188 24.03 65 1.287 25.04 70 1.386 25.86 75 1.485 26.38 80 1.584 26.79 85 1.683 26.96 90 1.782 27.00 95 1.881 26.86 100 1.980 26.53 quantum efficiency vs. wavelength 0 5 10 15 20 25 30 35 40 45 50 350 450 550 650 750 wavelength (nm) quantum effic iency ( % ) MT9M012 cra design 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 0 10 20 30 40 50 60 70 80 90 100 110 image height (%) cra (degrees) pdf: 3846173010/source: 5724337828 aptina reserves the right to change products or specifications without notice. MT9M012_ds - rev. d 5/10 en 50 ?2007 aptina imaging corporation. all rights reserved. MT9M012: 1/4.5-inch 1.6mp cmos digital image sensor electrical specifications advance electrical specifications two-wire serial register interface the electrical characteristics of the two- wire serial register interface (sclk, s data ) are shown in figure 23 and table 15. figure 23: two-wire serial bus timing parameters notes: 1. read sequence: for an 8-bit read, read waveforms start after write command and register address are issued. table 15: two-wire serial bus characteristics symbol parameter condition min typ max unit f sclk serial interface input clock frequency C C C 400 khz t sclk serial input clock period C 2.5 C C s sclk duty cycle C 40 50 60 % tr_sclk sclk rise time C C ns tf_sclk sclk fall time C C ns tr_sdat s data rise time C C ns tf_sdat s data fall time C C ns t srth start hold time write/read ns t sdh s data hold write ns t sds s data setup write ns t shaw s data hold to ack write ns t ahsw ack hold to s data write ns t stps stop setup time write/read ns t stph stop hold time write/read ns t shar s data hold to ack read ns t ahsr ack hold to s data read ns t sdhr s data hold read ns t sdsr s data setup read ns c in _ si serial interface input pin capacitance C C C pf c load _ sd s data max load capacitance C C C 15 pf r sd s data pull-up resistor C C 1500 C sdata sclk write start ack stop sdata sclk read start ack tr_clk tf_clk 90% 10% tr_sdat tf_sdat 90% 10% t sdh t sds t shaw t ahsw t stps t stph register address bit 7 write address bit 0 register value bit 0 register value bit 7 read address bit 0 register value bit 0 write address bit 7 read address bit 7 t shar t sdsr t sdhr t ahsr t srth t sclk pdf: 3846173010/source: 5724337828 aptina reserves the right to change products or specifications without notice. MT9M012_ds - rev. d 5/10 en 51 ?2007 aptina imaging corporation. all rights reserved. MT9M012: 1/4.5-inch 1.6mp cmos digital image sensor electrical specifications advance i/o timing by default, the MT9M012 launches pixel data, fv and lv with the rising edge of pixclk. the expectation is that the user captures d out [11:0], fv and lv using the falling edge of pixclk. see figure 24 and table 16 for i/o timing (ac) characteristics. figure 24: parallel i/o timing diagram notes: 1. pll disabled for t cp. table 16: i/o timing characteristics notes: 1. value equal to jitter on tester. symbol parameter condition min typ max unit f extclk input clock frequency pll disabled 8 C 49.5 mhz t extclk input clock period pll disabled 20.2 C 125 ns extclk clock duty cycle 40 50 60 % f pixclk output clock frequency pll enabled 8 C 49.5 mhz t pixclk output clock period pll enabled 20.2 C 125 ns pixclk clock duty cycle 40 50 60 % t r input clock rise time C v/ns t f input clock fall time C v/ns t rp pixclk rise time C v/ns t fp pixclk fall time C v/ns t (pix jitter) jitter on pixclk C C ps t jitter input clock jitter C C ps t cp extclk to pixclk propagation delay nominal voltages ns t pd pixclk to data valid default ns t pfh pixclk to fv high default ns t plh pixclk to lv high default ns t pfl pixclk to fv low default ns t pll pixclk to lv low default ns c load output load capacitance C C 10 pf c in input pin capacitance C 2.5 C pf data[11:0] frame_valid/ line_valid frame_valid leads line_valid by 354 pixclks. frame_valid trails line_valid by 16 pixclks. pixclk extclk t cp t r t extclk t f t rp t fp t pd t pd t pfh t plh t pfl t pll pxl _0 pxl _1 pxl _2 pxl _n 90% 10% 90% 10% pdf: 3846173010/source: 5724337828 aptina reserves the right to change products or specifications without notice. MT9M012_ds - rev. d 5/10 en 52 ?2007 aptina imaging corporation. all rights reserved. MT9M012: 1/4.5-inch 1.6mp cmos digital image sensor dc electrical characteristics advance dc electrical characteristics the dc electrical characteristics are shown in table 17. table 17: dc electrical characteristics symbol parameter condition min typ max unit v dd core digital voltage 1.7 1.8 1.9 v v dd _io i/o digital voltage 2.6 2.8 3.1 v v aa analog voltage 2.6 2.8 3.1 v vaa_pix pixel supply voltage 2.6 2.8 3.1 v v dd _pll pll supply voltage 2.6 2.8 3.1 v v ih input high voltage v dd _io= 2.8v v v il input low voltage v dd _io = 2.8v v i in input leakage current no pull-up resistor; v in = v dd _io or d gnd C <10 C a v oh output high voltage at specified i oh v v ol output low voltage at specified i ol v i oh output high current at specified v oh ma i ol output low current at specified v ol Cma i oz tri-state output leakage current v in = v dd _io or gnd C a i dd digital operating current streaming, full resolution C 28.0 ma i dd _io i/o digital operating current streaming, full resolution C 27.3 ma i aa analog operating current streaming, full resolution C 65.0 ma i aa _pix pixel supply current streaming, full resolution C 5.6 ma i dd _pll pll supply current streaming, full resolution C 3.0 ma i stby _a1 soft standby current clock off C 0.21 C ma i stby _b1 soft standby current clock off C 32.31 C ma i stby _a1 soft standby current clock off C 0.21 C ma i stby _b1 soft standby current clock off C 28.41 C ma table 18: power consumption (at 30 fps, full resolution, 25c) symbol definition typ current (ma) typ voltage (v) power (mw) p vdd digital operating power 28.0 1.8 50.4 p vddio 1 i/o digital operating power 7.7 2.8 21.6 p vddio 2 (d ata ) i/o power pixel data 19.6 2.8 86.5 p vaa analog operating power 65.0 2.8 182.0 p vaapix pixel supply power 5.6 2.8 15.7 p vddpll pll supply power 3.0 2.8 8.4 p total total power 364.6 pdf: 3846173010/source: 5724337828 aptina reserves the right to change products or specifications without notice. MT9M012_ds - rev. d 5/10 en 53 ?2007 aptina imaging corporation. all rights reserved. MT9M012: 1/4.5-inch 1.6mp cmos digital image sensor dc electrical characteristics advance absolute maximum ratings caution stresses greater than those listed in table 19 may cause permanent damage to the device. expo- sure to absolute maximum rating conditions for extended periods may affect reliability. notes: 1. this is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. table 19: absolute maximum values symbol parameter condition min max unit v dd _ max core digital voltage C0.3 1.9 v v dd _io_ max i/o digital voltage C0.3 3.1 v v aa _ max analog voltage C0.3 3.1 v vaa_pix_ max pixel supply voltage C0.3 3.1 v v dd _pll_ max pll supply voltage C0.3 3.1 v v in _ max input high voltage C0.3 v dd _io + 0.3 v i dd _ max digital operating current worst case current ma i dd _io_ max i/o digital operating current worst case current ma i aa _ max analog operating current worst case current ma i aa _pix_ max pixel supply current worst case current ma i dd _pll_ max pll supply current worst case current ma t op operating temperature measure at junction C30 70 c t stg storage temperature C40 85 c 10 eunos road 8 13-40, singapore post center, singapore 408600 prodmktg@aptina.com www.aptina.com aptina, aptina imaging, digitalclarity, and the aptina logo are the property of aptina imaging corporation all other trademarks are the property of their respective owners. advance: this data sheet contains initial descriptions of products still under development. MT9M012: 1/4.5-inch 1.6mp cmos digital image sensor revision history pdf: 3846173010/source: 5724337828 aptina reserves the right to change products or specifications without notice. MT9M012_ds - rev. d 5/10 en 54 ?2007 aptina imaging corporation all rights reserved. advance revision history rev. d . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5/10 ? updated to non-confidential rev. c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5/10 ? updated to aptina template rev. b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2/08 ? update table 1, ?key performance parameters,? on page 1 ? update "applications" on page 1 ? update"functional overview" on page 6 ? update table 3, ?signal descriptions,? on page 8 ? update "row timing details" on page 14 ? update figure 9: ?1280x720/30 fps row timing details,? on page 14 ? update figure 10: ?1440x1080/15 fps mode,? on page 14 ? update "features" on page 37 ? update "pll-generated master clock" on page 37 ? update "pll setup" on page 37 ? update table 8, ?frequency parameters,? on page 38 ? table 16, ?i/o timing characteristics,? on page 51 rev. a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8/07 ?initial release |
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